The first decade of 21st century has been passing its first half. In the semiconductor technology evolution, research and development toward 65nm technology has already been launched. According to the International Technology Roadmap for Semiconductors 2003 edition(ITRS 2003), mass production on 45nm technology will be started in 2010. Thus, we will get 4X integration capacity compared to 90nm technology. And, various kind of difficult challenges with respect to design may be accompanied by this technology evolution.
Particularly for designing System LSIs, difficult challenges become more hard, so that we need to cope with those problems not only in national cooperation but also extending the collaboration to the world wide organization.
The EDA Technical Committee(EDA-TC) is a part of the Japan Electronics and Information Technology Industries Association (JEITA) and is involved in a number of electronic design automation (EDA) related activities. Emphasis is placed especially on activities LSI design technologies which affects the functionality and performance of electronic devices. Our EDA-TC activities focuses on three themes. The first theme is the investigation and study of trends and information related to LSI design technology and proposing solutions to issues. This year, work is focused on research project titled as the Physical Design Methodology (PDM) research group. PDM research group is investigating and proposing solutions to issues raised by the move to System-On-Chip design and the move to 90-65nm processes. The second theme is contributing to EDA related standardization efforts by providing support to standards related groups and organizations. And, through the work of the standardization sub-committee organized under the EDA-TC, we are making technical proposals and promoting exchanges with international standardization efforts such as IEEE, IEC, etc. It is specially mentioned that we started the SystemC task group and the SystemVerilog task group last year, which dedicates to the language standardization related activities to SystemC and SystemVerilog, respectively.
The third theme is organizing and supporting events to promote and encourage EDA technology and standards. In fiscal 2003 year, we have sponsored the "Electronic Design and Solutions Fair 2004". The "EDS Fair" is an exhibition of design technologies for a broad range of electronic devices. We will take place "Electronic Design and Solutions Fair 2005" at the Pacifico Yokohama in January 2005.
In this way and through a variety of activities, our EDA-TC is continuing to contribute to the electronic equipment industry in the System-On-Chip toward 65nm through 45nm technology era from a design technology point of view. In addition, the 21 companies and approximately 40 staff and volunteers on the committee are planning through this autonomous venture to surmount the global upheavals which the System-On-Chip era will bring to our industry and further the development of the Japanese and Global electronics industries. It is our desire that, this year too, we will vigorously expand our activities and continue to forge our way towards the bright future beyond the System-On-Chip era.
