ก Background and objective
New design problems have been arisen in practical use of recent nano-meter semiconductor device and interconnect technology. In order to solve them, it becomes important to standardize design techniques or libraries that have been developed by each company. The standardization can reduce the development time and support cost, through creating excellent design environment as well as providing efficient communication between semiconductor manufacturers, customers and EDA venders.
Based on the background, our working group focuses on the following research subjects. The work will contribute on realizing new efficient design environments.
- To investigate problems on physical/statistical design and verification issues in next technology node LSI development.
- To develop fundamental concept of design rules and guidelines in deep nano-meter LSI design. It is utilized to specify library exchange format between semiconductor manufacturer, customer and EDA venders.
- To develop specific physical/statistical design and verification techniques. To propose standardization method of design libraries and information format, which allows secure improvement and compatibility of design precision.
- To provide benchmarking data, which achieve precise verification of the libraryfs performance and effectiveness.
ก Activities
Activities were started in May, 2007. The following themes have been conducted including their investigation, analysis and benchmarking during the 2014 fiscal year.
- EMI Noise Analysis
- Variation evaluation in the low voltage.
- Study on the physical design subject in next-generation transistor structure.
In 2015 fiscal year, NDP-SWG merges DFM subcommittee of SMTJ and expands the activities.
Based on the activities, the following reports and papers have been disclosed from NPD-SWG under JEITA organization.
- Annual report
- The homepage of JEITA
- Submitting papers to Conferences/Transactions.
Members: 10 committee members from 5 companies. Chair: Hiroaki Ammo /Sony Corp.