EDA Standardization Technical Sub- Committee 

EDA Standardization Technical Sub-Committee ( EDA-stdsc )

The mission of the EDA Standardization Technical Sub-committee is to support and promote the standardization activity of the international organizations, such as IEC/TC93, IEEE/DASC, IEEE-SA, Accellera, Si2, from the standpoint of the Japanese electronic industry.

Specifically, examination of the proposals, vote on various bills from the related organization, election and recommendation of the technical experts who investigate standardization proposals, etc. are performed.
In addition, the EDA Standardization Technical Sub-committee enlightens the standardization activities and the EDA technical committee's activities.

In 2003 the SystemC working group (SCWG) and the SystemVerilog working group (SVWG) began their activities for the purpose of reviewing and promoting the standardization of SystemC and SystemVerilog, respectively as the Japanese industry.
The SCWG and SVWG investigated the proposed languages, pointed out dozens of issues and contributed a lot to the standardization of both languages as IEEE std. 1666 and IEEE std. 1800 at the end of 2005.
The Power Format working group (PFWG) began the activity in 2007. This WG investigated the two proposed Power Formats and enlightens the opinion of the Japanese electronic industry to the standardization organizations.
In 2010, the LSI-Package-Board Interoperable Design Process Working Group was launched. This WG investigates the current difficulties and will propose their solutions to realize the integrated design environment for LSI, package, and board.
(Note: SVWG and PFWG completed their objectives and disbanded in March 2009 and March 2010 respectively.）

The related international standardization organizations of EDA-stdsc
(1) IEC/TC93 (International Electrotechnical Commission/Technical Committee for design automation)
At present, 4 Working Groups are working actively. These are WG2: Hardware Description Language, WG6: Reusable Component Library, WG7: Systems Test Description Language, JWG11: Printed circuit board. Specifically, a chair and a lot of member of the EDA standardization technical sub-committee join to the WG2 and are heading WG2 activity.
The TC93 international meeting is held every year. A lot of member attended from this subcommittee, and reported an activity in Japan.
The process of IEC/IEEE Dual Logo is advancing toward standardization of in advance standardized specifications in IEEE. We applied Dual Logo process to SystemC and SystemVerilog which are the newest design description languages for the System LSI standardized in IEEE. And, we are also examining to apply the process to UPF (Unified Power Format).

The activity of IEC can be seen at the following Web Site.
http://www.iec.ch/

(2) Accellera
Accellera, which is the standardization organization, was founded in 2000 combining the VI which had promoted VHDL and the OVI which had promoted Verilog HDL. Its mission is to drive worldwide development and use of standards required by systems, semiconductor and design tools companies, which enhance a language-based design automation process.

Accellera was concentrating on standardization of SystemVerilog which strengthens the verification function, in addition to the standardization of the design description language (HDL), such as VerilogHDL or VHDL.
SystemVerilog was standardized as IEEE std.1800-2005 in November, 2005.
And recently, UPF was standardized as IEEE std. 1801-2009.
The EDA-TC pointed out a few tens of issues in the proposed standard, and contributed very much to the final standard which reflects the opinion of EDA-TC, Japanese industry.

The activity of Accellera can be seen at the following Web Site.
http://www.accellera.org/

(3) IEEE/DASC (Institute of Electrical and Electronic Engineers/Design automation standard committee), IEEE-SA
DASC (Design Automation Standards Committee) and SA (Standards Association) are organizations under the control of the IEEE, and play an important role in the standardization of the design automation related to the electricity and the electronics industry.

The EDA-TC is the formal member of IEEE-SA and we have a member of IEEE-DASC. We are promoting the standardization through checking the proposed standard, pointing out the issues in it and voting the final document reflected the Japanese industry's opinions.

The activity of IEEE/DASC can be seen at the following Web Sites.

http://www.eda.org/
http://standards.ieee.org/db/status/status.txt

Activities of SystemC Working Group

- Background and Objectives
SystemC has been utilized for developing SoCs efficiently as a system-level description language. On December 12, 2005, SystemC was approved as IEEE standard (IEEE Std. 1666-2005) and SystemC has become more popular.

The SystemC Working Group (SCWG) is the sole organization for SystemC standardization in Japan. SCWG's objectives are 1) to contribute to the international standardization of SystemC in cooperation with OSCI and IEEE P1666 Working Group and 2) to promote the SoC design methodologies using SystemC.

- Activities
SCWG was organized on October 2003, and has been working on the international standardization and the promotion of SystemC actively. SCWG's main activities are below:

1. SystemC Standardization
SCWG participated IEEE P1666 Working Group as a voting member and contributed to standardization of the IEEE Std. 1666-2005. In 2006-2008, SCWG reviewed of the draft version and the final version of the TLM 2.0 (Transaction Level Modeling 2.0) and reported on the issues of 14 total. In 2009, SCWG reviewed OSCI TLM 2.0 LRM which was released in July 2009. JEITA will vote on the standardization at the end of 2010.

2. SystemC Technical Survey and Study
SSCWG is doing a survey on SystemC TLM global trend about technology and utilization. And SCWG is studying a necessary standardization and promoting TLM utilization in Japan. SCWG reviewed the SystemC Synthesizable subset draft and is studying a necessary standardization and guideline. So far, SCWG published the "Behavioral Synthesis Style Guide Composition Requirement". SCWG released "The SystemC Design Methodology Manual".

3. SystemC Promotion
SCWG hosts a Japanese SystemC User Forum every year. It introduces SystemC update information by OSCI, and SCWG activities and SystemC case studies by Japanese user.

SCWG member: 8 companies/8 people + 1 special member + 1 adviser, Chair: Hiroshi Imai/Toshiba Corporation.

LSI-Package-Board (LPB) Interoperable Design Process Working Group

- Background and Objectives
The Interface timing in the system bus is getting marginal with increasing bus speed, and noise is getting large issue in the system operation such as signal integrity (SI), power integrity (PI) and EMI according with low voltage operation in core supply and IO interfaces. In addition cost competitiveness is key aspect to success in the market so that the cost performance to be optimized in overall components and materials in the product.
Traditionally LSI, package and board are designed individually based on the design guideline which are provided independently. But, it is difficult to meet the requirements in the design guideline with using lower cost materials, so the budget of each part in overall system should be decided based on the simulation results in design by design. The simulation and analysis should be done within the product development period. However, it has been taken the time and cost to set up the design and simulation, because there is no standard format in the interface.
LPB Interoperable Design Process Working Group is working for defining the unified format and methodology.

- Activities
July, 2009 Established LPB co-design preparation WG.
April, 2010 Expand the member and renamed LPB Interoperable Design Process WG as the official subcommittee of EDA-TC.

- Scope
*Issues
In the process of "feasibility study"-"artwork design"-"simulation/analysis", there are three key database,
1. netlist,
2. geometry data,
3. physical (electrical/thermal/stress) parameters and constraints.
Currently there is no standard format in each processes and each parts (LSI-Package-Board).
There are two aspects in this situation,
a. The format and method are not defined yet, so that each parties deiced those independently.
b. The interface format and method is decided by EDA vender.
*Focus
LPB Interoperable Design Process WG is working for making the proposal of unified format.

The results of LPB Interoperable Design Process WG discussion will be disclosed as public information and announced in the seminars or symposiums.

(Members) 16 companies, 1 university / 25 people
including Semiconductors, System makers, EDA and University
(Chair) Yoshinori Fukuba/Toshiba Corporation.

SystemVerilog Working Group
(The activities have been suspended in 2009.)

- Purpose
SystemVerilog is a design and verification language, that is the extension of the widely used LSI design language VerilogHDL.This was approved as IEEE standard 1800-2005 on November 9th, 2005.IEEE integrates VerilogHDL with IEEE1800.
The purposes of this working group are the contribution to the international standardization activity of SystemVerilog with Accelleraand IEEE 1800 Working Group from Japan, and diffusion of the design and verification methodology using SystemVerilog in Japan.

- Activities
In August, 2004, the working group submited 32 contents as "Issue Reports" including proposals to improve the language specifications to Accellera and IEEE p1800 WG, and since then, the working group was involved in the investigation to finally fix the language specification. In June, 2005, the working group participated the final ballot as an IEEE-SA member to approve the standard.

In May, 2007, the working group submited 35 contens as "Issue Reports" to IEEE p1800 WG, and since then, the working group was watching the progress of revision in 2009.

From 2005 till 2007, the working group will host three SystemVerilog User Forum as a program of System Design Forum that will be held with EDSFair to diffuse SystemVerilog.

PowerFormat Working Group
(The activities have been suspended in 2010.)

- Purpose
Today, there are two "standard" format to design a low power System-LSI, CPF(Common Power Format) and UPF(Unified Power Format). Many System-LSI designers use a tool-chain composed from several EDA vendor's tool, so two "standard" formats will cause some problems of conversion or compatibility. This working group contributes to the international standardization activity of the Power Format with paying attention to inter-operability between CPF and UPF to keep convenience of System-LSI designer.


- Activities
This working group was organized as "Power Format Study working group" on Oct. 2007. At the moment, both power format has been implementing to several EDA tools by EDA vendors. Even if the formats are unified to one, there will be disorder after 3 to 5 years to migrate to the new format. So we decided not to try to unify them to single format, but to try to keep their inter-operability as the first object.
We jointed the balloting of UPF V2.0 IEEE P1801 started on Oct '2008. Our members reviewd the draft mainly from keeping inter-operability against CPF point of view and proposed 13 feedbacks including inprovement, then 4 our proposals were accepted. We keep watching further direction of two formats.